diff options
| author | Tianhao Wang <shrik3@mailbox.org> | 2024-04-17 14:53:37 +0200 |
|---|---|---|
| committer | Tianhao Wang <shrik3@mailbox.org> | 2024-06-11 15:16:32 +0200 |
| commit | 716e39d3808595fda3749d5df1518ae58be4551e (patch) | |
| tree | 6fa6f80eca320aea254c921bc18865ae4fbb7dbd /boot/startup-x86_64.s | |
| parent | e5733c69740dc492fa82aed35861c40a770e9b50 (diff) | |
cgascr: init cursor in rust code
Diffstat (limited to 'boot/startup-x86_64.s')
| -rw-r--r-- | boot/startup-x86_64.s | 34 |
1 files changed, 1 insertions, 33 deletions
diff --git a/boot/startup-x86_64.s b/boot/startup-x86_64.s index dfc6262..4c4cc21 100644 --- a/boot/startup-x86_64.s +++ b/boot/startup-x86_64.s @@ -9,7 +9,7 @@ ;*----------------------------------------------------------------------------* ;* The 'startup' function is the entry point for the whole system. Switching * ;* to 32-bit Protected Mode has already been done (by a boot loader that runs * -;* before). Here we prepare everything to be able to start running C++ code * +;* before). Here we prepare everything to be able to start running rust code * ;* in 64-bit Long Mode as quickly as possible. * ;****************************************************************************** @@ -20,9 +20,6 @@ ; stack for the main function (renamed to _entry()) STACKSIZE: equ 65536 -; video memory base address -CGA: equ 0xB8000 - ; 512 GB maximum RAM size for page table ; DON'T MODIFY THIS UNLESS YOU UPDATE THE setup_paging accordingly MAX_MEM: equ 512 @@ -191,7 +188,6 @@ clear_bss: ; initialize IDT and PICs call setup_idt call reprogram_pics - call setup_cursor fninit ; activate FPU @@ -298,34 +294,6 @@ setup_idt: ret ; -; make cursor blink (GRUB disables this) -; - -setup_cursor: - mov al, 0x0a - mov dx, 0x3d4 - out dx, al - call delay - mov dx, 0x3d5 - in al, dx - call delay - and al, 0xc0 - or al, 14 - out dx, al - call delay - mov al, 0x0b - mov dx, 0x3d4 - out dx, al - call delay - mov dx, 0x3d5 - in al, dx - call delay - and al, 0xe0 - or al, 15 - out dx, al - ret - -; ; Reprogram the PICs (programmable interrupt controllers) to have all 15 ; hardware interrupts in sequence in the IDT. ; |
