diff options
| author | Tianhao Wang <shrik3@mailbox.org> | 2024-06-04 23:37:37 +0200 |
|---|---|---|
| committer | Tianhao Wang <shrik3@mailbox.org> | 2024-06-11 15:17:12 +0200 |
| commit | 1b6934bbb1501deab6132138d361256fa7332846 (patch) | |
| tree | 9c18d9273fbb8dcfd729c744ca1b6926cc720539 | |
| parent | 648a36811a03d4e6428f8301018122f38d15d180 (diff) | |
pic: replace hardcoded values, add docs
Signed-off-by: Tianhao Wang <shrik3@mailbox.org>
| -rw-r--r-- | src/arch/x86_64/interrupt/pic_8259.rs | 37 |
1 files changed, 26 insertions, 11 deletions
diff --git a/src/arch/x86_64/interrupt/pic_8259.rs b/src/arch/x86_64/interrupt/pic_8259.rs index d40d5ba..98573f5 100644 --- a/src/arch/x86_64/interrupt/pic_8259.rs +++ b/src/arch/x86_64/interrupt/pic_8259.rs @@ -6,6 +6,7 @@ const IMR1: u16 = 0x21; const IMR2: u16 = 0xa1; const CTRL1: u16 = 0x20; const CTRL2: u16 = 0xa0; +const PIC_VECTOR_OFFSET: u8 = 0x20; pub struct PicDeviceInt; impl PicDeviceInt { @@ -13,19 +14,33 @@ impl PicDeviceInt { pub const KEYBOARD: u8 = 1; } -// init must be called before interrupt is enabled. +// code and text from: https://wiki.osdev.org/8259_PIC#Code_Examples +// reprogram the PIC; _init must be called before interrupt is enabled. // TODO: turn pic into a singleton struct +// TODO: replace these hardcoded .... +// 0x20: PIC1 COMMAND (MASTER) +// 0x21: PIC1 DATA +// 0xA0: PIC2 COMMAND (SLAVE) +// 0xA1: PIC2 DATA pub fn _init() { - outb(0x20, 0x11); - outb(0xa0, 0x11); - outb(0x21, 0x20); - outb(0xa1, 0x28); - outb(0x21, 0x04); - outb(0xa1, 0x02); - outb(0x21, 0x03); - outb(0xa1, 0x03); - outb(0xa1, 0xff); - outb(0x21, 0xfb); + // ICW1_ICW4 | ICW1_INIT + // start init sequence in cascade mode + outb(CTRL1, 0x11); + outb(CTRL2, 0x11); + // ICW2: MASTER PIC vector offset = 0x20 + outb(IMR1, PIC_VECTOR_OFFSET); + // ICW2: SLAVE PIC vector offset = 0x28 + outb(IMR2, PIC_VECTOR_OFFSET + 8); + // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100) + outb(IMR1, 0x04); + // ICW3: tell Slave PIC its cascade identity (0000 0010) + outb(IMR2, 0x02); + // ICW4: 8086 mode | auto (normal) EOI + outb(IMR1, 0x03); + outb(IMR2, 0x03); + // set masks + outb(IMR1, 0xfb); + outb(IMR2, 0xff); } // 8-bit registers IMR1 and IMR2 registers hold interrupt masking bit 0~7 and |